Altera PCI Compiler - Manual (Page 274)

7–6 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Functional Overview
PCI Bus Arbiter
The PCI-Avalon bridge has an optional, integrated PCI bus arbiter that
can be used in both the PCI Master/Target Peripheral and the PCI
Host-Bridge Device operating modes. When using the PCI bus arbiter,
the PCI-Avalon bridge will be automatically connected to requests and
grants for device zero.
Other PCI-Avalon Bridge Modules
The remaining PCI-Avalon bridge modules contain embedded memory
blocks, PCI MegaCore control modules, and bridge logic. These modules
provide the circuitry to enable the bridge’s functionality, i.e., transaction
translation, clock domain crossing, and transaction ordering.
PCI Operational Modes
The targeted Altera device can operate in any one of the following modes:
■ PCI Target-Only Peripheral
■ PCI Master/Target Peripheral
■ PCI Host-Bridge Device
1 MAX II devices only support the PCI Target-Only Peripheral
mode and only Single-Cycle Transfers Only performance
profile.
PCI Target-Only Peripheral Mode Operation
Figure 7–2 shows the block diagram of the PCI-Avalon bridge managing
the connectivity of the PCI Target-Only Peripheral mode with the
Single-Cycle Transfers Only performance profile. The configuration uses
the Non-Prefetchable Master port and has a Host processor and bus
arbiter on the PCI bus side. In the Single-Cycle Transfers Only
performance profile, all PCI transactions are transferred via the
Non-prefetchable Avalon-MM master port including access to
prefetchable BARs.