Altera PCI Compiler - Manual (Page 127)

Altera Corporation User Guide Version 11.1 3–53
October 2011
Functional Description
Burst Memory Read Target Transactions
The sequence of events for a burst memory read target transaction is the
same as that of a single-cycle memory read target transaction. However,
during a burst read transaction, more data is transferred and both the
local-side design and the PCI master can insert waits states at any point
during the transaction.
Figure 3–8 illustrates a burst memory read target
transaction. The 64-bit extension signals are not applicable to the
pci_mt32
and pci_t32 MegaCore functions.
The transaction shown in Figure 3–8 is a 64-bit zero-wait state burst
transaction with four data phases. The local side transfers five quad
words (QWORDs) in clock cycles 6 through 10. The PCI MegaCore function
transfers data to the PCI side in clock cycles 7 through 10. Because of the
PCI MegaCore function’s zero-wait state requirement, the PCI side reads
ahead from the local side. Also, because the l_beno bus is not available
until after a local data phase has completed, the delay between data
transfers on the local side and PCI side requires the local target device to
supply valid data on all bytes. If the local side is not prefetchable (i.e.,
reading ahead will result in lost or corrupt data), it must not accept burst
read transactions, and it should disconnect after the first QWORD transfer
on the local side. Additionally,
Figure 3–8 shows the lt_tsr[9] signal
asserted in clock cycle 4 because the master device has framen and
irdyn
signals asserted, thus indicating a burst transaction.
A burst transaction is indicated by the PCI MegaCore function if it detects
both irdyn and framen are asserted on the PCI side after the address
phase. The PCI MegaCore function asserts lt_tsr[9] to indicate a burst
transaction. The function asserts lt_tsr[9] if both irdyn and framen
are asserted during a valid target transaction. If lt_tsr[9] is not
asserted during a transaction, it indicates that irdyn and framen have
not been detected or asserted during the transaction. Typically this
situation indicates that the current transaction is single-cycle. However,
this situation is not guaranteed because it is possible for the master to
delay the assertion of irdyn in the first data phase by up to 8 clock cycles.
In other words, if lt_tsr[9] is asserted during a valid target
transaction, it indicates that the impending transaction is a burst, but if
lt_tsr[9]
is not asserted it may or may not indicate that the transaction
is single-cycle.