Altera PCI Compiler - Manual (Page 131)

Altera Corporation User Guide Version 11.1 3–57
October 2011
Functional Description
Mismatched Bus Width Memory Read Target Transactions
The following description applies only to the pci_mt64 and pci_t64
MegaCore functions handling mismatched bus width memory read
target transactions.
When using the pci_mt64 or pci_t64 MegaCore functions to accept
32-bit memory read transactions, the local side data bus width is 64 bits
while the PCI data bus width is 32 bits. The pci_mt64 and pci_t64
functions handle this bus width mismatch and automatically perform
DWORD
alignment.
The pci_mt64 and pci_t64 functions always assume a 64-bit local side
data bus width during memory read transactions. The functions read 64-
bit data (QWORD, or two DWORDs) and automatically transfer one DWORD at
a time to the PCI side. For the first PCI data phase, the pci_mt64 and
pci_t64
also perform automatic DWORD alignment, depending on the
PCI starting address of the transaction.
If the address of the transaction is a QWORD boundary
(ad[2..0] == B"000"), the first DWORD transferred to the PCI side is
the low DWORD, and pci_mt64 or pci_t64 assert both l_ldat_ackn
and l_hdat_ackn to indicate that the PCI MegaCore function will
transfer both DWORDs that were transferred on the local side. However, if
the address of the transaction is not at a QWORD boundary (ad[2..0] ==
B"100"
), the first DWORD transferred to the PCI side is the high DWORD.
The low DWORD is not transferred to the PCI side. The pci_mt64 and
pci_t64
functions deassert l_ldat_ackn and assert l_hdat_ackn
during the first data transfer on the local side to indicate that only the
high DWORD is transferred to the PCI side.
Figure 3–11 shows a 32-bit single-cycle mismatched bus width memory
read target transaction, which applies to the pci_mt64 and pci_t64
functions. Refer to
Figure 3–7 for the description of a 32-bit single-cycle
memory read transaction using the pci_mt32 and pci_t32 functions.
The sequence of events in Figure 3–11 is exactly the same as in Figure 3–7 ,
except for the following cases:
■ During the address phase (clock cycle 3), the master does not assert
req64n
because the transaction is 32 bits
■ The pci_mt64 or pci_t64 function does not assert ack64n when
it asserts devseln
■ The local side is informed that the pending transaction is 32 bits
because lt_tsr[7] is not asserted while lt_framen is asserted