Altera PCI Compiler - Manual (Page 72)

2–14 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Variation File Parameters
15 DISABLE_LAT_TMR (1) 1 Disable master latency timer. This bit controls
whether the latency timer circuitry will operate as
indicated in the PCI Local Bus Specification,
version 3.0. When this bit is set to 0, the latency
timer circuitry will operate normally and will force
the
pci_mt64 or pci_mt32 master to
relinquish bus ownership as soon as possible
when the latency timer has expired and
gntn is
not asserted. If this bit is set to 1, the latency timer
circuitry is disabled. In this case, the
pci_mt64
or pci_mt32 master will relinquish bus
ownership normally when the local side signal
lm_lastn
is asserted or when the target
terminates the PCI transaction with a retry,
disconnect, or abort.
16 PCI_64BIT_SYSTEM 0 64-bit only PCI devices. This bit allows enhanced
master capabilities when the pci_mt64 function
is used in systems where a 64-bit master request
will always be accepted by a 64-bit target device
(target device always responds with
ack64n
asserted). When this bit is set to 1, the pci_mt64
master will:
Support 64-bit single-cycle master write
transactions
Assert
irdyn one clock cycle after the assertion
of framen for read and write transactions.
This option should only be used in embedded
applications where the designer controls the
entire system configuration. This option does not
affect target transactions and does not affect
master 32-bit transactions including transactions
using the
lm_req32n , configuration, and I/O
transactions.
Table 2–2. Bit Definition of the ENABLE_BITS Parameter (Part 4 of 5)
Bit
Number
Bit Name
Default
Value
Definition