Altera PCI Compiler - Manual (Page 346)

8–16 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Simulation Flow
Refer to Figure 8–1 for a block diagram of the Master Transactor
model instantiated in the PCI testbench.
3. The master transactor defines the procedures (VHDL) or tasks
(Verilog HDL) needed to initiate PCI transactions in your testbench.
Add the commands that correspond to the transactions you want to
implement in your tests to the master transactor model source code.
At a minimum, you must add configuration commands to set the
BAR for the target transactor model and write the configuration
space of the PCI MegaCore function. Additionally, you can add
commands to initiate memory or I/O transactions to the PCI
MegaCore function.
Refer to Table 8–4 on page 8–7 for more information about the user
commands.
4. Compile the files in your simulator, including the testbench
modules and the files created by SOPC Builder.
5. Simulate the testbench for the desired time period.