Altera PCI Compiler - Manual (Page 41)

Altera Corporation User Guide Version 11.1 1–7
October 2011 PCI Compiler
Getting Started
Step 2: Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog
HDL model file produced by the Quartus II software. The model allows
for fast functional simulation of IP using industry-standard VHDL and
Verilog HDL simulators.
c Only use these simulation model output files for simulation
purposes and expressly not for synthesis or any other purposes.
Using these models for synthesis creates a nonfunctional design.
1 Some third-party synthesis tools can use a netlist that contains
only the structure of the MegaCore function, but not detailed
logic, to optimize performance of the design that contains the
MegaCore function. If your synthesis tool supports this feature,
turn on Generate netlist.
To generate an IP functional simulation model for your MegaCore
function, follow these steps:
1. Click Step 2: Set Up Simulation in IP Toolbench.
2. Turn on Generate Simulation Model.
3. Choose Verilog HDL in the Language list.
4. Click OK.
Step 3: Generate
Generate your MegaCore function after specifying parameter values and
IP functional simulation model options.
1 Clicking Quartus II Constraints displays up-to-date
information about PCI Constraint files.
f
For more information on PCI constraint files, refer to Appendix A, Using
PCI Constraint File Tcl Scripts .