Altera PCI Compiler - Manual (Page 280)

7–12 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Functional Overview
Within each of the PCI operating modes, the targeted Altera device can
use any of the performance profiles; the performance profiles are slightly
different per device operating mode.
Target Performance
The PCI-Avalon bridge provides the following three target performance
options:
■ Single-Cycle Transfers Only
■ Burst Transfers with Single Pending Read
■ Burst Transfers with Multiple Pending Reads
Single-Cycle Transfers Only
This profile uses the least amount of resources and does not require
embedded RAM blocks. This profile provides low latency and low
bandwidth connectivity for Avalon-MM slave peripherals. Only the
Non-Prefetchable Avalon-MM master port is enabled.
Burst Transfers With Single Pending Read
This profile allows high throughput read/write operations to
Avalon-MM slave peripherals. Read/write accesses to prefetchable base
address registers (BARs) use dual-port buffers to enable burst
transactions on both the PCI and Avalon-MM sides. This profile also
allows access to non-prefetchable PCI BARs to use the Non-prefetchable
Avalon-MM master port to initiate single-cycle transfers to Avalon-MM
slave peripherals. All PCI read transactions are completed as delayed
reads. However, only one delayed read is accepted and processed at a
time.
Burst Transfers With Multiple Pending Reads
This profile is exactly the same as the target Burst Transfers with Single
Pending Read performance profile except that it allows up to four
pending reads to be simultaneously processed.
Master Performance
The PCI-Avalon bridge provides the following two master performance
options:
■ Burst Transfers with Single Pending Read
■ Burst Transfers with Multiple Pending Reads