Altera PCI Compiler - Manual (Page 275)

Altera Corporation User Guide Version 11.1 7–7
October 2011
Functional Description
Figure 7–2. PCI-Avalon Bridge Managing the PCI Target-Only Peripheral Mode, Single-Cycle Transfers Only
Figure 7–3 shows the block diagram of the PCI-Avalon bridge managing
the connectivity of the PCI Target-Only Peripheral mode with either the
Burst Transfers with Single-Pending Read profile or the Burst Transfers
With Multiple Pending Reads performance profile. The configuration
uses two of the four Avalon-MM ports and has a Host processor and bus
arbiter on the PCI side.
1 Because both the Prefetchable and Non-Prefetchable
Avalon-MM master ports are instantiated, the Avalon bridge
must have at least two memory BARs; one prefetchable memory
BAR and one non-prefetchable memory BAR.
PCI-Avalon Bridge
Target-Only Peripheral Mode
With Single-Cycle Transfers Only
PCI
Target
Controller
PCI
Non-
Prefetchable
Bridge Logic
PCI
MegaCore
Function
System
Interconnect
Fabric
Avalon
Slave
Peripheral
Host
Processor
PCI
Master/
Target
Device
PCI
Bus
Arbiter
PCI
Bus
Non-
Prefetchable
Avalon
Master