Altera PCI Compiler - Manual (Page 60)

2–2 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Read-Only PCI Configuration Registers
Read-Only PCI
Configuration
Registers Parameters for read-only PCI configuration space registers are defined on
the Read-Only PCI Configuration Registers page of the Parameterize -
PCI Compiler
wizard.
The following read-only PCI configuration space register parameters are
set on this page:
■ Device ID
■ Vendor ID
■ Revision ID
■ Subsystem ID
■ Subsystem Vendor ID
■ Minimum Grant
■ Maximum Latency
■ Class Code
The parameters require hexadecimal values. For information on the
functionality of the read-only registers, refer to
“Configuration Registers”
on page 3–28 .
PCI Base
Address
Registers
(BARs) The PCI MegaCore functions implement up to six 32-bit BARs and an
expansion ROM BAR. The pci_mt64 and pci_t64 MegaCore functions
can also implement one 64-bit BAR using either BAR 1 and BAR0, or
BAR2 and BAR1.
You must instantiate at least one BAR in your application design.
Multiple BARs must be implemented in sequence starting from BAR0. By
default, BAR0 is enabled and reserves 1 MByte of memory space.
In addition to allowing normal BAR operation where the system writes
the base address value during system initialization, the PCI MegaCore
functions allow the base address of any BAR to be hardwired using the
Hardwire BAR
option. When hardwiring a BAR, the BAR address
becomes a read-only value supplied to the PCI MegaCore function
through the parameter value. System software cannot overwrite a base
address register that is hardwired. The value provided for the hardwired
BAR is written into the BAR, including the four least significant bits.
Thus, you must provide the appropriate value for all of the contents of the
BAR.
1 Use hardwired BARs in closed systems only.
The PCI BAR attributes are defined on the Base Address Registers
(BARs)
page of the Parameterize - PCI Compiler wizard.