Altera PCI Compiler - Manual (Page 313)

Altera Corporation User Guide Version 11.1 7–45
October 2011
Functional Description
PCI Host-Bridge
Operation You can use the PCI Host-Bridge Device operating mode when the host
processor resides on the Avalon-MM side. The PCI Host processor is
responsible for configuring all of the PCI devices. In PCI Host-Bridge
Device mode, the PCI-to-Avalon bridge operates the same as the PCI
Master mode except for the following situations:
■ The Control Register Access Avalon Slave port is no
longer optional.
■ The PCI command register’s bus master enable bit is hardwired to 1
to enable PCI master operations at power up.
■ You must connect the PCI-Avalon bridge’s idsel signal to one of the
address bus signals to enable self configuration.
Typically, you will need to implement the PCI bus arbitration logic.
However, you can still use any of the provided options for the PCI bus
arbitration. Refer to
“PCI Bus Arbiter” on page 7–6 .
Connecting the idsel signal to one of the ad(31:11) bus lines is an
operation that is not automatically performed when using the
PCI-Avalon bridge. This can be done in your top level Quartus II design
or you can use a resistive coupling on the board. Generating PCI
configuration transactions that access the PCI-Avalon bridge’s
configuration space is accomplished in the same way that all
configuration transactions are initiated.
Altera-Provided
PCI Bus Arbiter The Altera-provided arbiter can be enabled from the PCI Compiler
wizard. In addition, you can choose to support from two up to eight PCI
devices.
The number of external ports for the Altera-provided arbiter is dependent
on the number of supported PCI devices. The arbiter’s external ports are:
ArbReq_n_i[(N-1):1]
and ArbGnt_n_o[(N-1):1], where N is the
number of devices specified. The ArbReq_n_i[0] and
ArbGnt_n_o[0]
will automatically be connected to the PCI-Avalon
bridge’s reqn and gntn signals respectively.
1 If you choose to support two devices, the PCI test bench will be
automatically configured. If you choose to support more than
two devices, additional manual configuration is necessary.
The arbiter is a fair, single level arbiter. Once an ArbGnt_n_o signal is
asserted in response to the corresponding ArbReq_n_i, the grant is
maintained at least until one of the following occurs:
■ framen transitions from deasserted to asserted
■ 16 cycles elapse with framen deasserted
■ The corresponding ArbReq_n_i is deasserted