Altera PCI Compiler - Manual (Page 154)

3–80 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Target Mode Operation
Figure 3–24 shows an example of a disconnect during a burst write
transaction that ensures only a single data phase is completed.
Figure 3–24 applies to all PCI MegaCore functions, excluding the 64-bit
extension signals as noted for pci_mt32 and pci_t32. In Figure 3–24
1t_rdyn is asserted in clock cycle 5 and 1t_discn is asserted in clock
cycle 6. This transaction informs the PCI MegaCore function that the local
side is ready to accept data but also wants to disconnect. As a result, the
PCI MegaCore function disconnects after one data phase.
Figure 3–24. Single Data Phase Disconnect in a Burst Write Transaction
Note to Figure 3–24 :
(1) This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions.
ad[31..0]
(1) ad[63..32]
cben[3..0]
(1) cben[7..4]
par
(1) par64
framen
(1) req64n
irdyn
devseln
(1) ack64n
trdyn
stopn
lt_framen
l_adro[31..0]
l_cmdo[3..0]
lt_rdyn
lt_ackn
l_dato[31..0]
lt_dxfrn
(1) l_ldat_ackn
(1) l_hdat_ackn
clk
(1) l_dato[63..32]
l_beno[3..0]
(1) l_beno[7..4]
lt_tsr[11..0]
Adr
7
Adr-PAR
Adr
7
BE0_H
000 381
D0_L
D0_H
D0_L
D0-L-PAR
D0-H-PAR
BE0_L
000 381 781
D0_H
2 3 4 5 6 7 9 10 11 8 1
D1-L
D1_H
lt_discn
BE1_L
BE1_H
D1-L-PAR
D1-H_PAR
BE0_L
BE0_H