Altera PCI Compiler - Manual (Page 198)

3–124 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Master Mode Operation
Figure 3–45. 32-Bit PCI & 64-Bit Local-Side Master Burst Memory Write Transaction
I/O & Configuration Write Master Transactions
I/O and configuration write transactions by definition are 32 bits wide.
The sequence of events is the same as in a 32-bit single-cycle memory
write master transaction, as shown in
Figure 3–43 . This figure applies to
both the pci_mt64 and pci_mt32 MegaCore functions, excluding the
64-bit extension signals as noted for pci_mt32.
2 3 4 5 6 7 9 10 12
clk
reqn
8 11 1
gntn
ad[31..0]
cben[3..0]
par
framen
req64n
irdyn
devseln
ack64n
trdyn
stopn
Adr
7
Adr-PAR
BE_L
D0_L 0
0
13
lm_req64n
lm_lastn
lm_adr_ackn
lm_rdyn
lm_tsr[9..0] 000 001 004 002 108 008 000
l_ldat_ackn
l_hdat_ackn
lm_ackn
lm_dxfrn
D0-L-PAR
Z
Z
14
D1_H D0_H D1_L
D1-H-PAR D0-H-PAR D1-L-PAR
l_adi[31..0] Adr
7
l_adi[63..32] D0_H
D0_L D1_L
D1_H
l_cbeni[3..0] BE_L
l_cbeni[7..4] BE_H