Altera PCI Compiler - Manual (Page 118)

3–44 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Target Mode Operation
Maximum Latency Register
The maximum latency register is an 8-bit read-only register that defines
the frequency in which the function would like to gain access to the PCI
bus. Refer to
Table 3–33 . You can set this register through the wizard.
Target Mode
Operation This section describes all supported target transactions for the PCI
MegaCore functions. Although this section includes waveform diagrams
showing typical PCI cycles in target mode for the pci_mt64 MegaCore
function, these waveforms are also applicable for the pci_mt32,
pci_t64
, and pci_t32 MegaCore functions. The pci_mt64 and
pci_t64 MegaCore functions support both 32-bit and 64-bit
transactions. Table 3–34 lists the PCI and local side signals that apply for
each PCI function.
Table 3–33. Maximum Latency Register Format
Data Bit Mnemonic Read/Write Definition
7..0 max_lat Read Maximum latency register
Table 3–34. PCI MegaCore Function Signals (Part 1 of 3)
Signal Name pci_mt64 pci_t64 pci_mt32 pci_t32
PCI Signals
clk v v v v
rstn v v v v
gntn v v
reqn v v
ad[63..0] v v ad[31..0] ad[31..0]
cben[7..0] v v cben[3..0] cben[3..0]
par v v v v
par64 v v
idsel v v v v
framen v v v v
req64n v v
irdyn v v v v
devseln v v v v
ack64n v v