Altera PCI Compiler - Manual (Page 186)

3–112 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Master Mode Operation
6 The PCI MegaCore function begins the 64-bit memory write transaction with the address phase by
asserting
framen and req64n .
At the same time, the local side must provide the byte enables for the transaction on the l_cbeni
bus. You can change the byte enables for the successive data words in burst transactions by turning
on Allow Variable Byte Enable During Burst Transactions option in the Advanced PCI
MegaCore Function Features page of the Parameterize - PCI Compiler wizard. Refer to
“Allow
Variable Byte Enables During Burst Transactions” on page 2–5 for more information about this
opti on.
The PCI MegaCore function asserts lm_ackn to indicate to the local side that it is ready to transfer
data. Because lm_rdyn was asserted in the previous cycle and lm_ackn is asserted in the current
cycle, the PCI MegaCore function asserts lm_dxfrn . The assertion of the lm_dxfrn and
l_hdat_ackn signals indicate to the local side that the PCI MegaCore function has transferred one
data word from the l_adi bus.
The function asserts lm_tsr[2] to indicate to the local side that the PCI bus is in its address phase.
If the arbiter deasserts gntn in less than 3 clock cycles, the PCI MegaCore function does not assert
lm_tsr[2] in this clock cycle. For recommendations of how to accommodate scenarios where the
arbiter deasserts gntn in less than three clock cycles, refer to “Design Consideration” on page 3–92
for more information.
7 The target claims the transaction by asserting devseln . In this case, the target performs a fast
address decode. The target also asserts ack64n to inform the function that it can transfer 64-bit
data. The target also asserts trdyn to inform the function that it is ready to receive data.
During this clock cycle, the function also asserts lm_tsr[3] to inform the local side that it is in data
phase mode. The function deasserts lm_ackn because its internal pipeline has valid data from the
local side data transfer during the previous clock cycle but no data was transferred on the PCI side.
To ensure that the proper data is transferred on the PCI bus, the function asserts
irdyn during the
first data phase only after the PCI target asserts devseln .
8 The function asserts irdyn to inform the target that the function is ready to send data. Because the
irdyn and trdyn are asserted, the first 64-bit data is transferred to the PCI side on the rising edge
of clock cycle 9.
The PCI MegaCore function asserts lm_tsr[9 ] to indicate to the local side that the target can
transfer 64-bit data. The function also asserts lm_ackn to inform the local side that the PCI side is
ready to accept data. Because lm_rdyn was asserted in the previous cycle and lm_ackn is
asserted in the current cycle, the function asserts lm_dxfrn . The assertion of the lm_dxfrn ,
l_ldat_ackn , and l_hdat_ackn signals indicates to the local side that it has transferred one
data word from the l_adi bus.
Table 3–39. Zero-Wait State Burst Memory Write Master Transaction (Part 2 of 3)
Clock
Cycle
Event