Altera PCI Compiler - Manual (Page 113)

Altera Corporation User Guide Version 11.1 3–39
October 2011
Functional Description
For example, if a 64-bit BAR on BARs 1 and 0 is implemented and the
designer indicates 8 as the maximum number of address bits to decode
on the upper BAR, the upper 24 bits [31..8] of BAR1 will be read-only
bits tied to ground. The eight least significant bits [7..0] of BAR1 are
read/write registers, and— along with bits [31..4] of BAR0—they
indicate the size of the memory. When a 64-bit memory BAR is
implemented, the remaining BARs can still be used for 32-bit memory or
I/O base address registers in conjunction with a 64-bit BAR setting. If
BARs 2 and 1 are used to implement a 64-bit BAR, BAR0 must be used as
a 32-bit memory or I/O base address register.
1 Reserved memory space can be calculated by the following
formula: 2
(40 – 8) = 4 GBytes, where 40 = actual available registers
and 8 = user assigned read/write register.
Like a memory BAR, an I/O BAR can be instantiated on any of the six
BARs available for the PCI function. The wizard offers the option to
implement a 32-bit BAR as memory or I/O and sets the bits [1..0] of
the corresponding BARn parameter accordingly. The PCI Local Bus
Specification, Revision 3.0 prevents any single I/O BAR from reserving
more than 256 bytes of I/O space. Refer to
Table 3–24 .
In some applications, one or more BARs must be hardwired. The PCI
MegaCore functions allow you to set default base addresses that can be
used to claim transactions without requiring the configuration of the
corresponding BARs. The wizard allows you to implement this feature on
an individual BARn basis and sets the corresponding parameters
accordingly. When using the hardwire BAR feature, the corresponding
BARn attributes must indicate the appropriate BAR settings, such as size
and type of address space.
1 When implementing a hardwire BAR, the corresponding BARs
become read-only. A configuration write to the hardwired BAR
will proceed normally. However, a configuration read of
hardwired BARs will return the value set in the hardwire BARn
parameter.
Table 3–24. I/O Base Address Register Format
Data
Bit
Mnemonic Read/Write Definition
0 io_ind Read I/O indicator. The io_ind bit indicates that the register maps into I/O
address space. This bit must be set to 1 in the BARn parameter.
1 Reserved – –
31..2 bar Read/write Base address registers.