Altera PCI Compiler - Manual (Page 286)

7–18 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
PCI Target Operation
To ensure the lowest possible latency, the PCI-Avalon bridge can handle
just one PCI-to-Avalon, non-prefetchable request at a time. A single
command register holds the command, address, and byte enables for
either the current read or the current write operation. If the register is still
busy with the previous operation, no additional read or write requests are
accepted and a retry is signaled on the PCI interface.
Non-Prefetchable Write Operations
The non-prefetchable bridge data path handles both the memory write
command and the memory write and invalidate command if they hit
either:
■ A non-prefetchable BAR.
■ A prefetchable BAR when the Single-Cycle Transfers Only target
performance profile is selected.
■ An I/O BAR.
When PCI write requests are claimed from the PCI bus, they are passed
to Avalon-MM as write requests. Both PCI memory write and PCI
memory write and invalidate PCI bus commands are treated identically
inside the non-prefetchable PCI-Avalon bridge logic. The first data phase
worth of data is accepted from the PCI bus and written to the
PCI-to-Avalon write data register. A target disconnect is signaled as the
first data phase is accepted from the PCI bus.
The PCI-to-Avalon address translation circuit is used to compute the
appropriate Avalon-MM address. The non-prefetchable Avalon-MM
master port will then issue a single-cycle Avalon-MM write transaction to
transfer data.
Table 7–4 shows all of the possible termination conditions for
non-prefetchable PCI target write operations.
Table 7–4. Non-Prefetchable Write Operation
Termination Condition Resulting Action
PCI-to-Avalon non-prefetchable command already in
progress The target controller retries the operation on the PCI
bus. Nothing is remembered about the retried PCI write
operation. When the PCI write operation is
subsequently re-issued, it is treated as a new
operation.
Normal master initiated termination of single data
phase transaction Data is accepted and written to the PCI-to-Avalon
non-prefetchable data register and then written to
Avalon.