Altera PCI Compiler - Manual (Page 206)

3–132 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
64-Bit Addressing, Dual Address Cycle (DAC)
64-Bit Address, 64-Bit Data Single-Cycle Target Read Transaction
Figure 3–48 shows the waveform for a 64-bit address, 64-bit data single-
cycle target read transaction. Figure 3–48 is exactly the same as
Figure 3–7 , except that Figure 3–48 has two address phases (described in
the previous paragraph). Also, both lt_tsr[1..0] signals are asserted
to indicate that the BAR0 and BAR1 address range of pci_mt64 and
pci_t64
matches the current transaction address. In addition, the
current transaction upper 32-bit address is latched on l_adro[63..32],
and the lower 32-bit address is latched on l_adro[31..0].
1 All 32-bit addressing transactions described in “Target Mode
Operation” on page 3–131 are applicable for 64-bit addressing
transactions, except for the differences described in the previous
paragraph.