Altera PCI Compiler - Manual (Page 301)

Altera Corporation User Guide Version 11.1 7–33
October 2011
Functional Description
Single-cycle, 64-bit Avalon-to-PCI read requests that have only the upper
or lower 32 bits enabled, need to be issued as single-cycle, 32-bit read
requests on the PCI bus.
Avalon-MM requires that read response data be returned in the order
requested. Typically, read requests on PCI are initially retried. Usually, a
PCI master will issue additional PCI reads after one has been retried—this
routine is done so that the PCI targets can start the internal actions for
servicing the reads in parallel. However, this leaves the PCI master with
little control over the order in which the reads complete. In bridging to
Avalon-MM, this can be a particular problem when a PCI read is issued
and gets retried, while a second read is issued and data is immediately
provided. The bridge needs to hold on to that data until data for the first
read is returned.
To solve this problem with the best possible performance, the PCI-Avalon
bridge has four Avalon-to-PCI read response buffers for holding pending
reads. The multiple response buffers are used when the Burst Transfers
with Multiple Pending Reads performance profile is chosen.
There is also a buffer for holding additional Avalon-to-PCI read
commands before they are allocated to a pending read buffer and issued
on the PCI bus. This buffer allows writes to pass reads before they are
allocated an Avalon-to-PCI read response buffer.
When a PCI read request is read from the Avalon-to-PCI bypassable read
buffer, it is assigned to the first available Avalon-to-PCI read response
buffer. If an Avalon-to-PCI read response buffer is not available, the PCI
read request is held in the Avalon-to-PCI bypassable read buffer.
To return the read data to Avalon-MM in the correct order, the
Avalon-MM side of the Avalon-to-PCI read response buffers is always
read from the buffers in a first-in, first-out order.
No attempt is made to combine multiple Avalon-MM reads to
consecutive locations into a single PCI Read burst.
Table 7–11 shows PCI master read request termination conditions.
Table 7–11. PCI Master Read Request Termination Conditions (Part 1 of 2)
Termination Condition Resulting Action
Burst count satisfied Normal master initiated termination on the PCI bus. Master controller proceeds to the
next command.
Latency timer expired Normal master initiated termination on PCI bus. The continuation of the PCI read is
made pending as a request the master controller arbiter.