Altera PCI Compiler - Manual (Page 213)

Altera Corporation User Guide Version 11.1 4–3
October 2011 PCI Compiler
Testbench
Table 4–1 gives a description of the PCI testbench source files provided in
the tb_src directory. For more information on these files, refer to
“Testbench Specifications” on page 4–6 .
Table 4–1. Files Contained in the tb_src Directory
File (1) Description
mstr_tranx The master transactor defines the procedures
(VHDL) or tasks (Verilog HDL) needed to initiate PCI
transactions in the testbench.
mstr_pkg The master package consists descriptions of
procedures (VHDL) or tasks (Verilog HDL) of the
master transactor (mstr_tranx) commands.
trgt_tranx The target transactor simulates the target behavior in
the testbench. It serves to respond to PCI
transactions.
trgt_tranx_mem_init.dat This file is the memory initialization file for the target
transactor.
monitor This module monitors the PCI transactions on the
bus and reports the results.
clk_gen This module generates 33-or 66-MHz clock for the
PCI agents.
arbiter This module contains PCI bus arbiter.
pull_up This module is used to provide weak pull-up on the
tri-stated signals.
altera_tb This is a sample top-level file that instantiates the
testbench modules and the IP functional simulation
model of the PCI MegaCore function. You can use
this sample top-level file in your application design by
replacing the
top_local instance from the
testbench file with the top level of your application
design. Refer to
“Simulation Flow” on page 4–20 for
more information.
Note to Table 4–1 :
(1) All files are provided in both VHDL and Verilog HDL.