Altera PCI Compiler - Manual (Page 177)

Altera Corporation User Guide Version 11.1 3–103
October 2011
Functional Description
Single-Cycle Memory Read Master Transaction
Figure 3–35 shows a 64-bit single-cycle memory read master transaction.
Figure 3–35 shows the same transaction as in Figure 3–31 with just one
data phase. This figure applies to both the pci_mt64 and pci_mt32
MegaCore functions, excluding the 64-bit extension signals as noted for
pci_mt32
. In clock cycle 6, framen and req64n are asserted to begin
the address phase. At the same time, the local side should assert the
lm_lastn
signal on the local side to indicate that it wants to transfer only
one 64-bit data word. In a real application, in order to indicate a single-
cycle 64-bit data transfer, the lm_lastn signal can be asserted on any
clock cycle between the assertion of lm_req64n and the address phase.
1 If your application is a system that has only 64-bit PCI devices
and the local side wants to transfer one 64-bit data word, Altera
recommends that you perform a 64-bit single-cycle memory
read master transaction. However, if your application is a
system that has 32-bit and 64-bit PCI devices and the local side
wants to transfer one 64-bit data word, Altera recommends that
you perform a 32-bit burst memory read transaction.