Altera PCI Compiler - Manual (Page 156)

3–82 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Target Mode Operation
Figure 3–26 shows an example of a disconnect during a burst read
transaction that ensures only a single data phase is completed. In
Figure 3–26 , lt_rdyn is asserted in clock cycle 5 and lt_discn is
asserted in clock cycle 6. This transaction informs the PCI MegaCore
function that the local side is ready with data but also wants to
disconnect. As a result the PCI MegaCore function disconnects after one
data phase. This figure applies to all PCI MegaCore functions, excluding
the 64-bit extension signals as noted for pci_mt32 and pci_t32.
Figure 3–26. Single Cycle Disconnect in a Burst Read Transaction
Note to Figure 3–26 :
(1) This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions.
ad[31..0]
(1) ad[63..32]
cben[3..0]
(1) cben[7..4]
par
(1) par64
framen
(1) req64n
irdyn
devseln
(1) ack64n
trdyn
stopn
l_adro[31..0]
l_cmdo[3..0]
l_adi[31..0]
clk
(1) l_adi[63..32]
Adr
6
Adr-PAR
Z
Z
BE0_L
BE0_H
Z
D0_L
D0_H
D0_L
D0_H
D0-L-PAR
D0-H-PAR
2 3 4 5 6 7 9 10 8 11 1
Adr
6
lt_framen
lt_ackn
lt_dxfrn
lt_rdyn
lt_discn
lt_tsr[11..0] 000 381 000 381 781