Figure 3–16 – Altera PCI Compiler User Manual
Page 142
3–68
User Guide Version 11.1
Altera Corporation
PCI Compiler
October 2011
Target Mode Operation
Figure 3–16. Zero-Wait State Burst Memory Write Target Transaction
(1)
This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions.
ad[31..0]
(1) ad[63..32]
cben[3..0]
(1) cben[7..4]
par
(1) par64
framen
(1) req64n
irdyn
devseln
(1) ack64n
trdyn
stopn
lt_framen
l_adro[31..0]
l_cmdo[3..0]
lt_rdyn
lt_ackn
l_dato[31..0]
lt_dxfrn
(1) l_ldat_ackn
(1) l_hdat_ackn
clk
(1) l_dato[63..32]
l_beno[3..0]
(1) l_beno[7..4]
lt_tsr[11..0]
Adr
7
Adr-PAR
Adr
7
BE0_L
BE0_H
000
381
781
D0_L
D0_H
D0_L
D0-L-PAR
D0-H-PAR
BE0_L
000
D1_L
D1_H
D2_L
D2_H
D3_L
D3_H
D1_L
D1_H
D2_L
D2_H
D3_L
D3_H
D1-L-PAR
D1-H-PAR
D2-L-PAR
D2-H-PAR
D3-L-PAR
D3-H-PAR
D0_H
D4_L
D4_H
D4-L-PAR
D4-H-PAR
2
3
4
5
6
7
9
10
12
8
11
1
13
14
D4_L
D4_H
BE1_L
BE1_H
BE2_L
BE2_H
BE3_L
BE3_H
BE4_L
BE4_H
BE1_L
BE1_H
BE2_L
BE2_H
BE3_L
BE3_H
BE4_L
BE4_H
BE0_H