Altera PCI Compiler - Manual (Page 28)

16 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Performance and Resource Utilization
Table 11 lists memory utilization and performance data for MAX II
devices.
1
MAX II devices only support the PCI Target-Only peripheral
and the single-cycle performance setting.
PCI
Master/
Target Min Typical 2,715 7 50 3,668 10 89 >67
Typical Typical 3,053 9 50 4,187 14 89 >67
Max Typical 3,540 9 50 4,682 14 89 >67
Min Max 3,728 10 50 5,138 16 89 >67
Typical Max 4,059 12 50 5,634 20 89 >67
Max Max 4,788 14 50 6,696 22 89 >67
Notes to Table 10 :
(1) Min = Single-cycle transactions
Typical = Burst transactions with a single pending read
Max = Burst transactions with multiple pending reads
(2) In Cyclone devices, memory is implemented in M4K blocks, not M512 blocks.
(3) The data was obtained by performing compilations on a Cyclone EP1C20F400C7 device. Each of the device types
was parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side. For the PCI
Master/Target Peripheral mode, one MByte of memory was reserved on the PCI side.
Table 10. Memory Utilization & Performance Data for Stratix, Stratix GX & Cyclone Devices (3) (Part 2
of 2)
PCI
Device
Mode
Performance Setting as: (1) 32-Bit PCI Interface 64-Bit PCI Interface
PCI
f
MAX
(MHz)
PCI Target PCI Master
Logic
Elements
(LEs)
M512
Memory
Blocks
(2)
I/O
Pins
Logic
Elements
(LEs)
M512
Memory
Blocks
(2)
I/O
Pins
Table 11. Memory Utilization & Performance Data for MAX II Devices (2)
PCI
Device
Mode
Performance Setting as: (1) 32-Bit PCI Interface
PCI f
MAX
(MHz)
PCI Target PCI Master
Logic
Elements
(LEs)
Memory
Blocks
I/O Pins
PCI
Target-Only Min N/A 770 0 48 >67
Notes to Table 11 :
(1) Min = Single-cycle transactions
(2) The data was obtained by performing compilations on a MAX II EPM2210F324C3 device. The device type was
parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side.