Altera PCI Compiler - Manual (Page 103)

Altera Corporation User Guide Version 11.1 3–29
October 2011
Functional Description
Table 3–12 shows the defined 64-byte configuration space. The registers
within this range are used to identify the device, control PCI bus
functions, and provide PCI bus status. The shaded areas indicate registers
that are supported by the PCI MegaCore functions.
Table 3–13 summarizes the supported configuration registers address
map. Unused registers produce a zero when read, and they ignore a write
operation. Read/write refers to the status at run time, i.e., from the
perspective of other PCI bus agents. You can set some of the read-only
registers when creating a custom PCI design by using the IP Toolbench
Parameterize - PCI Compiler
wizard. For example, you can change the
Table 3–12. PCI Bus Configuration Registers
Address
Byte
3 2 1 0
0x00 Device ID Vendor ID
0x04 Status Register Command Register
0x08 Class Code Revision ID
0x0C BIST Header Type Latency Timer Cache Line
Size
0x10 Base Address Register 0
0x14 Base Address Register 1
0x18 Base Address Register 2
0x1C Base Address Register 3
0x20 Base Address Register 4
0x24 Base Address Register 5
0x28 Card Bus CIS Pointer
0x2C Subsystem ID Subsystem Vendor ID
0x30 Expansion ROM Base Address Register
0x34 Reserved Capabilities
Pointer
0x38 Reserved
0x3C Maximum
Latency
Minimum Grant Interrupt Pin Interrupt Line