Altera PCI Compiler - Manual (Page 272)

7–4 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Functional Overview
This port is optimized for high bandwidth transfers as a PCI target and is
optional for PCI master/target peripherals that do not need to support
burst transactions as a PCI target.
This port is enabled when you perform both of the following:
■ Select one of the following target performance settings:
● Burst Transfers with Single Pending Read
● Burst Transfers with Single or Multiple Pending Reads
■ Implement at least one prefetchable BAR
Non-Prefetchable Avalon-MM Master
The Non-Prefetchable Avalon-MM Master port provides a low latency
PCI memory request access to Avalon-MM slave peripherals. Burst
operations are not supported on this master port. Only the exact amount
of data needed to service the initial data phase will be read from the
interconnect. Therefore, the PCI byte enables (for the first data phase of
the PCI read transaction) are passed directly to the interconnect.
This Avalon-MM master port is also optimized for low latency access
from PCI-to-Avalon-MM slaves. This is optimal for providing PCI target
access to simple Avalon-MM peripherals. This port is optional for
implementations that do not need non-prefetchable access to peripherals.
If you select Single-Cycle Transfers Only target performance profile, this
port will be the only Avalon-MM master port instantiated.
PCI Bus Access Slave
This Avalon-MM slave port is used to propagate the following
transactions from the interconnect to the PCI bus:
■ Single cycle memory read and write requests
■ Burst memory read and write requests
■ I/O read and write requests
■ Configuration read and write requests
Burst requests from the interconnect are the only way to create burst
transactions on the PCI bus.
This slave port is not implemented in the PCI Target-Only Peripheral
mode.
Control Register Access Avalon-MM Slave
This Avalon-MM slave port is available to all three PCI device modes and
is used to access various control and status registers in the PCI-Avalon
bridge. To provide external PCI master access to these registers, one of the