Altera PCI Compiler - Manual (Page 106)

3–32 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Configuration Registers
Command Register
Command is a 16-bit read/write register that provides basic control over
the ability of the PCI function to respond to the PCI bus and/or access it.
Refer to
Table 3–16 .
Table 3–16. Command Register Format
Data
Bit
Mnemonic Read/Write Definition
0 io_ena Read/write I/O access enable. When high, io_ena lets the function respond to
the PCI bus I/O accesses as a target.
1 mem_ena Read/write Memory access enable. When high, mem_ena lets the function
respond to the PCI bus memory accesses as a target.
2 mstr_ena Read/write Master enable. When high, mstr_ena allows the function to request
mastership of the PCI bus. Bit 2 is hardwired to 1 when PCI master
host bridge options are enabled through the wizard.
3 Unused – –
4 mwi_ena Read/write Memory write and invalidate enable. This bit controls whether the
master may generate a MWI command. Although the function
implements this bit, it is ignored. The local side must ensure that the
mwi_ena output is high before it requests a master transaction using
the MWI command.
5 Unused – –
6 perr_ena Read/write Parity error enable. When high, perr_ena enables the function to
report parity errors via the perrn output.
7 Unused – –
8 serr_ena Read/write System error enable. When high, serr_ena allows the function to
report address parity errors via the serrn output. However, to signal
a system error, the perr_ena bit must also be high.
9 Unused – –
10 int_dis Read/write Interrupt disable. A value of 1 disables the PCI MegaCore function
from asserting
intan on the PCI bus. However, the interrupt is only
disabled after the preexisting interrupt has been serviced.
15..11 Unused – –