Altera PCI Compiler - Manual (Page 167)

Altera Corporation User Guide Version 11.1 3–93
October 2011
Functional Description
Master Read Transactions
This section describes the behavior of the PCI MegaCore functions in the
following types of master read transactions:
■ Memory read
■ I/O and configuration read
Memory Read Transactions
The PCI MegaCore functions support the following types of matched bus
width and mismatched bus width memory read transactions in master
mode:
■ Burst memory read
■ Single-cycle memory read
■ Mismatched bus width memory read
1 Mismatched bus-width transactions are 32-bit PCI transactions
performed by the pci_mt64 MegaCore function.
For each type of transaction, the following sequence of events is the same:
1. The local side asserts lm_req32n to request a 32-bit transaction (or
lm_req64n
to request a 64-bit transaction.) Consequently, the PCI
side asserts reqn to request bus ownership from the PCI arbiter.
2. When the PCI arbiter grants bus ownership by asserting the gntn
signal, the PCI side asserts lm_adr_ackn on the local side to
acknowledge the transaction address and command. During the
same clock cycle when lm_adr_ackn is asserted, the local side
must provide the address on l_adi[31..0] and the command on
l_cbeni[3..0]
. At the same time, the PCI side turns on the
drivers for framen (and req64n for 64-bit transactions.)
3. The PCI side begins the PCI address phase. During the PCI address
phase, the local side must provide the byte enables for the
transaction on the l_cbeni bus. At the same time, the PCI side
turns on the driver for irdyn.
1 The PCI MegaCore function uses the initial byte enable values
throughout the transaction, and ignores any changes to the
signals on the l_cbeni bus after this phase. If the Allow
Variable Byte Enables During Burst Transactions
option is
turned on in the Parameterize - PCI Compiler wizard, you must
keep the byte enables constant throughout the transaction.
Typically the byte enable values are set to 0x00 for master read
transactions.