Altera PCI Compiler - Manual (Page 294)

7–26 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
PCI Target Operation
Table 7–8 lists the reasons for which a burst transfer can be terminated
and the resulting actions.
PCI-to-Avalon Address Translation
Figure 7–8 shows the PCI-to-Avalon address translation. The bits in the
PCI address that are used in the BAR matching process are replaced by an
Avalon-MM base address that is specific to that BAR. The Avalon-MM
base addresses are hardwired from the CB_P2A_AVALON_ADDR_B[0:5]
parameters for each BAR.
Table 7–8. Termination of Prefetchable Target Burst Reads
Termination Condition Resulting Action
Response buffer is empty and no more
data is expected from the interconnect The target controller issues a disconnect and the response buffer is
available for re-use.
Response buffer is empty, more data is
expected from the interconnect, and less
than eight cycles have elapsed since the
last data phase. Wait states are inserted on the PCI bus in an attempt to extend the
burst transaction.
Response buffer is empty, more data is
expected from the interconnect, and
eight cycles have elapsed since the last
data phase The target controller issues a target disconnect. The data is
discarded when returned from the interconnect, and the response
buffer is available for re-use after all expected data from the
interconnect is discarded.
Normal master completion ● Data in the response buffer is discarded.
● Data already requested from the interconnect is discarded when
returned.
● After all expected data from the interconnect is discarded, the
response buffer is available for re-use.
Prefetchable target burst read crosses
the BAR boundary One data phase worth of data is read and returned and the request is
disconnected. This happens when the burst count exceeds the PCI
BAR boundary (
Table 7–7 on page 7–24 ).
Prefetchable target burst read with
cacheline wrap mode One data phase worth of data is transferred and the request is
disconnected.
Target abort Not applicable. The target controller will not terminate a PCI write
operation with a target abort.