Altera PCI Compiler - Manual (Page 170)

3–96 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Master Mode Operation
Table 3–38 shows the sequence of events for a 64-bit zero-wait state burst
memory read master transaction. The 64-bit extension signals are not
applicable to the pci_mt32 function.
Table 3–38. Zero-Wait State Burst Memory Read Master Transaction (Part 1 of 3)
Clock
Cycle
Event
1 The local side asserts lm_req64n to request a 64-bit transaction.
2 The function outputs reqn to the PCI bus arbiter to request bus ownership. At the same time, the
function asserts lm_tsr [0] to indicate to the local side that the master is requesting the PCI bus.
3 The PCI bus arbiter asserts gntn to grant the PCI bus to the function. Although Figure 3–31 shows
that the grant occurs immediately and the PCI bus is idle at the time gntn is asserted, this action
may not occur immediately in a real transaction. Before the function proceeds, it waits for gntn to be
asserted and the PCI bus to be idle. A PCI bus idle state occurs when both framen and irdyn are
deasserted.
5 The function turns on its output drivers, getting ready to begin the address phase.
The function also asserts lm_adr_ackn to indicate to the local side that it must provide the address
and command for the transaction. During the same clock cycle, the local side must provide the PCI
address on
l_adi[31..0] and the PCI command on l_cbeni[3..0] .
The function continues to assert its reqn signal until the end of the address phase. The function also
asserts lm_tsr[1] to indicate to the local side that the PCI bus has been granted.
6
The function begins the 64-bit memory read transaction with the address phase by asserting
framen and req64n .
At the same time, the local side must provide the byte enables for the transaction on the l_cbeni
bus. The PCI MegaCore function uses this byte enable value throughout the transaction, and ignores
any changes to the signals on the
l_cbeni bus after this clock cycle. If the Allow Variable Byte
Enables During Burst Transactions option is turned on in the Parameterize - PCI Compiler
wizard, you must keep the byte enables constant throughout the rest of the transaction. Typically, the
byte enable values are set to 0x00 for master read transactions.
The local side also asserts lm_rdyn to indicate that it is ready to accept data.
The function asserts lm_tsr[2] to indicate to the local side that the PCI bus is in its address phase.
If the arbiter deasserts gntn in less than 3 clock cycles, the PCI MegaCore function does not assert
lm_tsr[2] in this clock cycle. For recommendations of how to accommodate scenarios where the
arbiter deasserts gntn in less than three clock cycles, refer to “Design Consideration” on page 3–92
for more information.