Document Outline

• Pinout (265)
  • Memory bus interface
  • Ethernet interface MAC
  • General purpose I/O (GPIO)
  • System clock
  • System mode
  • System reset
  • JTAG Test
  • ADC
  • POR and battery-backed logic
  • Power and ground
• I/O Control Module
  • Control and Status registers
  • GPIO Configuration registers
  • GPIO Control registers
  • GPIO Status registers
  • Memory Bus Configuration register
• Working with the CPU
  • Instruction sets
  • System control processor (CP15) registers
  • R0: ID code and cache type status registers
  • R1: Control register
  • R2: Translation Table Base register
  • R3:Domain Access Control register
  • R4 register
  • R5: Fault Status registers
  • R6: Fault Address register
  • R7:Cache Operations register
  • R8:TLB Operations register
  • R9: Cache Lockdown register
  • R10:TLB Lockdown register
  • R11 and R12 registers
  • R13:Process ID register
  • R14 register
  • R15: Test and debug register
  • Jazelle(Java)
  • DSP
  • MemoryManagement Unit (MMU)
  • MMU faults and CPU aborts
  • Domain access control
  • Fault checking sequence
  • External aborts
  • Enabling and disabling the MMU
  • TLB structure
  • Caches and write buffer
  • Cache MVA and Set/Way formats
  • Noncachable instruction fetches
• System Control Module
  • Bus interconnection
  • System bus arbiter
  • Address decoding
  • Programmable timers
  • General purpose timers/counters
  • Basic PWM function
  • Enhanced PWM function
  • Quadrature decoder function
  • How the quadrature decoder/counter works
  • Interrupt controller
  • Vectored interrupt controller (VIC) flow
  • Configurable system attributes
  • PLL configuration
  • Bootstrap initialization
  • System configuration registers
  • General Arbiter Control register
  • BRC0, BRC1, BRC2, and BRC3 registers
  • AHB Error Detect Status 1
  • AHB Error Detect Status 2
  • AHB Error Monitoring Configuration register
  • Timer Master Control register
  • Timer 0-4 Control registers
  • Timer 5 Control register
  • Timer 6-9 Control registers
  • Timer 6-9 High registers
  • Timer 6-9 Low registers
  • Timer 6-9 High and Low Step registers
  • Timer 6-9 Reload Step registers
  • Timer 0-9 Reload Count and Compare register
  • Timer 0-9 Read and Capture register
  • Interrupt Vector Address Register Level 31-0
  • Int (Interrupt) Config (Configuration) 31-0 registers
  • ISADDR register
  • Interrupt Status Active
  • Interrupt Status Raw
  • Software Watchdog Configuration
  • Software Watchdog Timer
  • Clock Configuration register
  • Module Reset register
  • Miscellaneous System Configuration and Status register
  • PLL Configuration register
  • Active Interrupt Level ID Status register
  • Power Management
  • AHB Bus Activity Status
  • System Memory Chip Select 0 Dynamic Memory Base and Mask registers
  • System Memory Chip Select 1 Dynamic Memory Base and Mask registers
  • System Memory Chip Select 2 Dynamic Memory Base and Mask registers
  • System Memory Chip Select 3 Dynamic Memory Base and Mask registers
  • System Memory Chip Select 0 Static Memory Base and Mask registers
  • System Memory Chip Select 1 Static Memory Base and Mask registers
  • System Memory Chip Select 2 Static Memory Base and Mask registers
  • System Memory Chip Select 3 Static Memory Base and Mask registers
  • Gen ID register
  • External Interrupt 0-3 Control register
  • RTC Module Control register
• Memory Controller
  • Low-power operation
  • Memory map
  • Static memory controller
  • Static memory initialization
  • Static memory read control
  • Static memory read: Timing and parameters
  • Asynchronous page mode read
  • Asynchronous page mode read: Timing and parameters
  • Static memory write control
  • Static memory Write: Timing and parameters
  • Bus turnaround
  • Bus turnaround: Timing and parameters
  • Byte lane control
  • Address connectivity
  • Dynamic memory controller
  • SDRAM Initialization
  • SDRAM address and data bus interconnect
  • Registers
  • Control register
  • Status register
  • Configuration register
  • Dynamic Memory Control register
  • Dynamic Memory Refresh Timer register
  • Dynamic Memory Read Configuration register
  • Dynamic Memory Precharge Command Period register
  • Dynamic Memory Active to Precharge Command Period register
  • Dynamic Memory Self-refresh Exit Time register
  • Dynamic Memory Last Data Out to Active Time register
  • Dynamic Memory Data-in to Active Command Time register
  • Dynamic Memory Write Recovery Time register
  • Dynamic Memory Active to Active Command Period register
  • Dynamic Memory Auto Refresh Period register
  • Dynamic Memory Exit Self-refresh register
  • Dynamic Memory Active Bank A to Active Bank B Time register
  • Dynamic Memory Load Mode register to Active Command Time register
  • Static Memory Extended Wait register
  • Dynamic Memory Configuration 0-3 registers
  • Dynamic Memory RAS and CAS Delay 0-3 registers
  • StaticMemory Configuration 0-3 registers
  • StaticMemory Write Enable Delay 0-3 registers
  • Static Memory Output Enable Delay 0-3 registers
  • Static Memory Read Delay 0-3 registers
  • StaticMemory Page Mode Read Delay 0-3 registers
  • Static Memory Write Delay 0-3 registers
  • StaticMemory Turn Round Delay 0-3 registers
• Ethernet Communication Module
  • Ethernet MAC
  • Station address logic (SAL)
  • Statistics module
  • Ethernet front-end module
  • Receive packet processor
  • Transmit packet processor
  • Ethernet slave interface
  • Interrupts
  • Resets
  • Multicast address filtering
  • Clock synchronization
  • Ethernet Control and Status registers
  • Ethernet General Control Register #1
  • Ethernet General Control Register #2
  • Ethernet General Status register
  • Ethernet Transmit Status register
  • Ethernet Receive Status register
  • MAC Configuration Register #1
  • MAC Configuration Register #2
  • Back-to-Back Inter-Packet-Gap register
  • Non Back-to-Back Inter-Packet-Gap register
  • Collision Window/Retry register
  • Maximum Frame register
  • MII Management Configuration register
  • MII Management Command register
  • MII Management Address register
  • MII Management Write Data register
  • MII Management Read Data register
  • MII Management Indicators register
  • Station Address registers
  • Station Address Filter register
  • RegisterHash Tables
  • Statistics registers
  • RX_A Buffer Descriptor Pointer register
  • RX_B Buffer Descriptor Pointer register
  • RX_C Buffer Descriptor Pointer register
  • RX_D Buffer Descriptor Pointer register
  • Ethernet Interrupt Status register
  • Ethernet Interrupt Enable register
  • TX Buffer Descriptor Pointer register
  • Transmit Recover Buffer Descriptor Pointer register
  • TX Error Buffer Descriptor Pointer register
  • TX Stall Buffer Descriptor Pointer register
  • RX_A Buffer Descriptor Pointer Offset register
  • RX_B Buffer Descriptor Pointer Offset register
  • RX_C Buffer Descriptor Pointer Offset register
  • RX_D Buffer Descriptor Pointer Offset register
  • Transmit Buffer Descriptor Pointer Offset register
  • RX Free Buffer register
  • Multicast Address Filter registers
  • Multicast Address Mask registers
  • Multicast Address Filter Enable register
  • TX Buffer Descriptor RAM
  • RX FIFO RAM
  • Sample hash table code
• External DMA
  • DMA transfers
  • DMA buffer descriptor
  • Descriptor list processing
  • Peripheral DMA read access
  • Peripheral DMA write access
  • Peripheral REQ and DONE signaling
  • Static RAM chip select configuration
  • Control and Status registers
  • DMA Buffer Descriptor Pointer
  • DMA Control register
  • DMA Status and Interrupt Enable register
  • DMA Peripheral Chip Select register
• AES Data Encryption/Decryption Module
  • AES DMA buffer descriptor
  • Decryption
  • ECB processing
  • CBC, CFB, OFB, and CTR processing
  • CCM mode
• I/O Hub Module
  • DMA controller
  • Transmit DMA example
  • Control and status register address maps
  • [Module] Interrupt and FIFO Status register
  • [Module] DMA RX Control
  • [Module] DMA RX Buffer Descriptor Pointer
  • [Module] RX Interrupt Configuration register
  • [Module] Direct Mode RX Status FIFO
  • [Module] Direct Mode RX Data FIFO
  • [Module] DMA TX Control
  • [Module] DMA TX Buffer Descriptor Pointer
  • [Module] TX Interrupt Configuration register
  • [Module] Direct Mode TX Data FIFO
  • [Module] Direct Mode TX Data Last FIFO
• Serial Control Module: UART
  • Normal mode operation
  • Baud rate generator
  • Hardware-based flow control
  • Character-based flow control (XON/XOFF)
  • Forced character transmission
  • ARM wakeup on character recognition
  • Wrapper Control and Status registers
  • Wrapper Configuration register
  • Interrupt Enable register
  • Interrupt Status register
  • Receive Character GAP Control register
  • Receive Buffer GAP Control register
  • Receive Character Match Control register
  • Receive Character-Based Flow Control register
  • Force Transmit Character Control register
  • ARM Wakeup Control register
  • Transmit Byte Count
  • UART Receive Buffer
  • UART Transmit Buffer
  • UART Baud Rate Divisor LSB
  • UART Baud Rate Divisor MSB
  • UART Interrupt Enable register
  • UART Interrupt Identification register
  • UART FIFO Control register
  • UART Line Control register
  • UART Modem Control register
  • UART Line Status register
  • UART Modem Status register
• Serial Control Module: HDLC
  • Receive and transmit operations
  • Clocking
  • Bits
  • Data encoding
  • Digital phase-locked-loop (DPLL) operation: Encoding
  • DPLL operation: Adjustment ranges and output clocks
  • Normal mode operation
  • Wrapper and HDLC Control and Status registers
  • Wrapper Configuration register
  • Interrupt Enable register
  • Interrupt Status register
  • HDLC Data Register 1
  • HDLC Data Register 2
  • HDLC Data register 3
  • HDLC Control Register 1
  • HDLC Control Register 2
  • HDLC Clock Divider Low
  • HDLC Clock Divider High
• Serial Control Module: SPI
  • SPI controller
  • SPI clocking modes
  • SPI clock generation
  • System boot-over-SPI operation
  • SPI Control and Status registers
  • SPI Configuration register
  • Clock Generation register
  • Interrupt Enable register
  • Interrupt Status register
  • SPI timing characteristics
• I2C Master/Slave Interface
  • Physical I2C bus
  • I2C external addresses
  • I2C command interface
  • I2C registers
  • Command Transmit Data register
  • Status Receive Data register
  • Master Address register
  • Slave Address register
  • Configuration register
  • Interrupt Codes
  • Software driver
  • Flow charts
• Real Time Clock Module
  • RTC configuration and status registers
  • RTC General Control register
  • 12/24 Hour register
  • Time register
  • Calendar register
  • Time Alarm register
  • Calendar Alarm register
  • Alarm Enable register
  • Event Flags register
  • Interrupt Enable register
  • Interrupt Disable register
  • Interrupt Enable Status register
  • General Status register
• Analog-to-Digital Converter (ADC) Module
  • ADC DMA procedure
  • ADC control and status registers
  • ADC Configuration register
  • ADC Clock Configuration register
  • ADC Output Registers 0-7
• Timing
  • Electrical characteristics
  • DC electrical characteristics
  • Reset and edge sensitive input timing requirements
  • Memory Timing
  • Reset and hardware strapping timing
  • JTAG timing
  • Clock timing
• Packaging
  • Package
  • Processor Dimensions
• Change log
  • Revision B
  • Revision C