2 functional description – Comtech EF Data CDM-625A User Manual

Page 47

Advertising
background image

CDM-625A Advanced Satellite Modem

MN-CDM625A

Introduction

Revision 3

1–3

1.2

Functional Description

The CDM-625A has two fundamentally different types of interface - IF and data:

• The IF interface provides a bidirectional link with the satellite via the uplink and downlink

equipment.

• The data interface is a bidirectional path that connects with the customer’s equipment

(assumed to be the DTE) and the modem (assumed to be the DCE).

Transmit data is received by the terrestrial interface where line receivers convert the clock and

data signals to CMOS levels for further processing. A small FIFO follows the terrestrial interface

to facilitate the various clocking and framing options. If framing is enabled, the transmit clock

and data output from the FIFO pass through the framer, where the overhead data (IDR, IBS, D&I

or EDMAC) is added to the main data; otherwise, the clock and data are passed directly to the

Forward Error Correction encoder.

In the FEC encoder, the data is differentially encoded, scrambled, and then convolutionally or

block encoded. Following the encoder, the data is fed to the transmit digital filters, which

perform spectral shaping on the data signals. The resultant in-phase (I) and quadrature (Q)

signals are then fed to the BPSK, QPSK/OQPSK, 8PSK, 8-QAM, 16-QAM, 8-ARY, 16-ARY, and 32-

ARY modulator.

The carrier is generated by a frequency synthesizer, and the I and Q signals directly modulate

this carrier. For L-Band applications, the directly modulated signal comprises the main output.

For IF applications (50–180 MHz), the L-Band signal is mixed down and filtered to produce the

desired output. The Rx-IF signal at L-Band is processed by a dual IF superheterodyne receiver.

For IF applications (50–180 MHz), the signal is first mixed up to the first IF frequency. The

second conversion is a complex mix, resulting in the signal once more being split into in-phase (I)

and a quadrature (Q) components, producing an output at near-zero frequency. An AGC circuit

maintains the desired signal level constant over a broad range. Following this, the I and Q signals

are sampled by high-speed (flash) A/D converters. All processing beyond this conversion is

purely digital, performing the functions of Nyquist filtering, carrier recovery, and symbol timing

recovery. The resultant demodulated signal is fed, in soft decision form, to the selected FEC

decoder, which can be Viterbi, Sequential, TCM, Reed-Solomon, TPC, LDPC, VersaFEC, or

VersaFEC-2.

After decoding, the recovered clock and data pass to the de-framer (if IBS, IDR, D&I or EDMAC

framing is enabled), where the overhead information is removed. Following this, the data passes

to the Plesiochronous/Doppler buffer, which has a programmable size, or may be bypassed.

From here, the receive clock and data signals are routed to the terrestrial interface, and are

passed to the externally connected DTE equipment.

Advertising