Altera Triple Speed Ethernet MegaCore Function User Manual
Page 115
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//AUTO_NEGOTIATION_ENA = 1, Bit 6,8,13 is Read Only
PCS Control Register = 0x1140
d. PCS Reset
//PCS Software reset is recommended where there any configuration changed
//RESET = 1
PCS Control Register = 0x9140
Wait PCS Control Register RESET bit is clear
3. MAC Configuration Register Initialization
Refer to step 2 in
Triple-Speed Ethernet System with MII/GMII or RGMII
on page 6-28.
If 1000BASE-X/SGMII PCS is initialized, set the
ETH_SPEED
(bit 3) and
ENA_10
(bit 25) in
command_config
register to 0. If half duplex is reported in the PHY/PCS status register, set the
HD_ENA
(bit 10) to 1 in
command_config
register.
Note:
Configuration Register Space
Altera Corporation
UG-01008
Triple-Speed Ethernet System with 1000BASE-X Interface
6-32
2014.06.30
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