Altera Triple Speed Ethernet MegaCore Function - Manual (Page 33)

Description Value Name
Turn on this option to include the logic for full-
duplex flow control that includes pause frames
generation and termination. On/Off Enable full-duplex flow
control
Turn on this option to include the logic for
VLAN and stacked VLAN frame detection.
When turned off, the MAC does not detect
VLAN and staked VLAN frames. The MAC
forwards these frames to the user application
without processing them. On/Off Enable VLAN detection
Turn on this option to include logic for magic
packet detection (Wake-on LAN). On/Off Enable magic packet detection
MDIO Module
Turn on this option if you want to access external
PHY devices connected to the MAC function.
When turned off, the core does not include the
logic or signals associated with the MDIO
interface. On/Off Include MDIO module
(MDC/MDIO)
Clock divisor to divide the MAC control
interface clock to produce the MDC clock output
on the MDIO interface. The default value is 40.
For example, if the MAC control interface clock
frequency is 100 MHz and the desired MDC
clock frequency is 2.5 MHz, a host clock divisor
of 40 should be specified.
Altera recommends that the division factor is
defined such that the MDC frequency does not
exceed 2.5 MHz.
— Host clock divisor
FIFO Options
The FIFO options are enabled only for MAC variations that include internal FIFO buffers.
Table 3-3: FIFO Options Parameters
Parameter Value Name
Width
Determines the data width in bits of the transmit
and receive FIFO buffers. 8 Bits and 32 Bits Width
Depth
Determines the depth of the internal FIFO
buffers.
Between 64 and 64K
Transmit
Receive
Parameter Settings Altera Corporation
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FIFO Options 3-4
2014.06.30