Altera Triple Speed Ethernet MegaCore Function - Manual (Page 175)

10 Testbench
2014.06.30
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You can use the testbench provided with the Triple-Speed Ethernet MegaCore function to exercise your
custom MegaCore function variation. The testbench includes the following features:
• Easy-to-use simulation environment for any standard HDL simulator.
• Simulation of all basic Ethernet packet transactions.
• Open source Verilog HDL and VHDL testbench files.
The provided testbench applies only to custom MegaCore function variations created using Qsys.
Triple-Speed Ethernet Testbench Architecture
Figure 10-1: Triple-Speed Ethernet Testbench Architecture
Device Under Test
Frame
Generator
System
Side
Ethernet
Side
Port 0
Port 2
Port n
..
.
Port 1
Frame
Monitor MDIO
Slave 0
MDIO
Slave 1
Testbench Control
Simulation Configuration Parameters
Testbench Components
The testbench comprises the following modules:
ISO
9001:2008
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