Altera Triple Speed Ethernet MegaCore Function - Manual (Page 3)

Ethernet MAC Options...............................................................................................................................3-2
FIFO Options................................................................................................................................................3-4
Timestamp Options.....................................................................................................................................3-5
PCS/Transceiver Options...........................................................................................................................3-5
Functional Description.......................................................................................4-1
10/100/1000 Ethernet MAC.......................................................................................................................4-1
MAC Architecture...........................................................................................................................4-2
MAC Interfaces................................................................................................................................4-3
MAC Transmit Datapath................................................................................................................4-4
MAC Receive Datapath...................................................................................................................4-7
MAC Transmit and Receive Latencies........................................................................................4-11
FIFO Buffer Thresholds................................................................................................................4-12
Congestion and Flow Control......................................................................................................4-16
Magic Packets.................................................................................................................................4-17
MAC Local Loopback....................................................................................................................4-18
MAC Error Correction Code.......................................................................................................4-19
MAC Reset......................................................................................................................................4-19
PHY Management (MDIO).........................................................................................................4-20
Connecting MAC to External PHYs...........................................................................................4-22
1000BASE-X/SGMII PCS With Optional Embedded PMA................................................................4-24
1000BASE-X/SGMII PCS Architecture......................................................................................4-25
Transmit Operation.......................................................................................................................4-26
Receive Operation..........................................................................................................................4-27
Transmit and Receive Latencies...................................................................................................4-28
SGMII Converter...........................................................................................................................4-28
Auto-Negotiation...........................................................................................................................4-29
Ten-bit Interface............................................................................................................................4-32
PHY Loopback...............................................................................................................................4-33
PHY Power-Down.........................................................................................................................4-33
1000BASE-X/SGMII PCS Reset...................................................................................................4-34
Altera IEEE 1588v2 Feature......................................................................................................................4-35
IEEE 1588v2 Supported Configurations.....................................................................................4-35
IEEE 1588v2 Features....................................................................................................................4-36
IEEE 1588v2 Architecture.............................................................................................................4-37
IEEE 1588v2 Transmit Datapath.................................................................................................4-37
IEEE 1588v2 Receive Datapath....................................................................................................4-38
IEEE 1588v2 Frame Format.........................................................................................................4-38
Altera Corporation
TOC-3 Triple-Speed Ethernet MegaCore Function User Guide