Altera Triple Speed Ethernet MegaCore Function - Manual (Page 159)

Figure 7-22: Egress Timestamp Insert for IEEE 1588v2 PTP Packet Encapsulated in IEEE 802.3
Egress Timestamp Insert, IEEE 1588v2, PTP Packet
2-step Timestamp Request,Input
tx_egress_timestamp_request_valid
tx_egress_timestamp_request_data[N:0]
2-step Timestamp Return,Output
tx_egress_timestamp_96b_valid
tx_egress_timestamp_96b_fingerprint[N:0]
tx_egress_timestamp_96b_data[95:0]
tx_egress_timestamp_64b_valid
tx_egress_timestamp_64b_fingerprint[N:0]
tx_egress_timestamp_64b_data[63:0]
1-step Timestamp Insert,Input
tx_etstamp_ins_ctrl_timestamp_insert
tx_etstamp_ins_ctrl_timestamp_format
1-step Residence Time Update,Input
tx_etstamp_ins_ctrl_residence_time_update
tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0]
tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0]
tx_etstamp_ins_ctrl_residence_time_calc_format
1-step IPv4 and IPv6 Checksum,Input
tx_etstamp_ins_ctrl_checksum_zero
tx_etstamp_ins_ctrl_checksum_correct
1-step Location Offset,Input
tx_etstamp_ins_ctrl_offset_timestamp[15:0] Offset 1
Don’t-care
Don’t-care
Don’t-care
Don’t-care
Don’t-care
Don’t-care
Don’t-care
Don’t-care
Don’t-care
Don’t-care
tx_etstamp_ins_ctrl_offset_correction_field[15:0] Offset 2
tx_etstamp_ins_ctrl_offset_checksum_field[15:0]
tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]
Figure 7-23 shows the TX timestamp signals for the first type of egress correction field update, where the
residence time is calculated by subtracting 96 bit ingress timestamp from 96 bit egress timestamp. The result
is updated in the correction field of the PTP frame encapsulated over UDP/IPv4.
The
tx_etstamp_ins_ctrl_residence_time_calc_format
signal is driven low to indicate that this is a
96b residence time calculation. The
tx_etstamp_ins_ctrl_checksum_zero
signal is driven high to clear
the UDP/IPv4 checksum field to all 0.
Interface Signals Altera Corporation
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IEEE 1588v2 Timestamp 7-44
2014.06.30