Altera Triple Speed Ethernet MegaCore Function - Manual (Page 127)

10/100/1000 Multiport Ethernet MAC Signals
Figure 7-2: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers Signals
Multi -Port MAC
PHY
Management
Signals
mdio _in
mdc
mdio _oen
mdio _out
Pause and Magic
Packet Signals
mac _tx_clk _n
mac _rx _clk _n
Clock
Signals
xon _gen _n
xoff _gen _n
magic _wakeup _n
magic _sleep _n_n
MAC
Status
Signals
set _10 _n
set _1000 _n
ena _10 _n
eth _mode _n
Reset
Signal
reset
Clock
Signals rx _clk _n
tx_clk _n
8
data _tx_data _n[7:0]
data _tx_eop _n
data _tx_error _n
data _tx_sop _n
data _tx_valid _n
data _tx_ready _n
MAC Transmit
Interface Signals
tx_crc _fwd _n
tx_ff_uflow _n
MAC Receive
Interface Signals
5
MAC Packet
Classification
Signals
pkt _class _valid _n
pkt _class _data _n[4:0]
n
rx _afull _channel [CHANNEL _WIDTH -1:0]
rx _afull _data [1:0]
rx _afull _valid
MAC FIFO
Status Signals
rx _afull _clk
4
4
MII
Signals
m
_rx _d_n[3:0]
m_rx _dv _n
m_rx _err _n
m_col _n
m_crs _n
m
_tx_d_n[3:0]
m_tx_en _n
m_tx_err _n
4
4
RGMII
Signals
rgmii _out _n[3:0]
tx_control _n
rgmii _in_n[3:0]
rx _control _n
8
8
GMII
Signals
gm _rx _d_n[7:0]
gm _rx _dv _n
gm _rx _err _n
gm _tx_d_n[7:0]
gm _tx_en _n
gm _tx_err _n
5
8
data _rx _data _n[7:0]
data _rx _eop _n
data _rx _sop _n
data _rx _error _n[4:0]
data _rx _ready _n
data _rx _valid _n
2
32
32
MAC Control
Interface
Signals
clk
reg _addr [7:0]
reg _rd
reg _wr
reg _data _out [31 :0]
reg _data _in[31 :0]
reg _busy
8
ECC Status
Signal
mac_eccstatus[1:0]
Multiport MAC Clock and Reset Signals
Table 7-13: Clock Signals
Description I/O Avalon-ST Signal
Type
Name
Receive MAC clock (2.5/25/125 MHz) for the
Avalon-ST receive data and receive packet
classification interfaces. O clk mac_rx_clk
Interface Signals Altera Corporation
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10/100/1000 Multiport Ethernet MAC Signals 7-12
2014.06.30