Altera Triple Speed Ethernet MegaCore Function - Manual (Page 178)

Simulation Model
This section describes the step-by-step instructions for generating the simulation model and simulating your
design using the ModelSim simulator or other simulators.
Generate the Simulation Model
The generated design example includes both Verilog HDL and VHDL testbench files for the device under
test (DUT)—your custom MegaCore function variation.
To generate a Verilog functional simulation model, use the command prompt and run the quartus_sh -t
generate_sim_verilog.tcl file. Alternatively, perform the following steps:
1. Launch the Quartus II software and browse to the <variation name>_testbench directory.
2. Open the generate_sim.qpf file from the project directory.
3. On the Tools menu, select Tcl Scripts and select the generate_sim_verilog.tcl file.
4. Click Run.
To generate a VHDL functional simulation model, you can use the command prompt and run the quartus_
sh -t generate_sim_vhdl.tcl file. Alternatively, perform the following steps:
1. Launch the Quartus II software and browse to the <variation name>_testbench directory.
2. Open the generate_sim.qpf file from the project directory.
3. On the Tools menu, select Tcl Scripts and browse to the generate_sim_vhdl.tcl file.
4. Click Run.
Simulate the IP Core
You can simulate your IP core variation with the functional simulation model and the testbench or design
example generated with your IP core. The functional simulation model and testbench files are generated in
a project subdirectory. This directory may also include scripts to compile and run the testbench.
For a complete list of models or libraries required to simulate your IP core, refer to the scripts provided with
the testbench in
Simulation Model Files on page 10-5.
Before you begin
Generate the simulation model as shown in Generate the Simulation Model on page 10-4 before simulating
the testbench design.
To use the ModelSim
®
simulation software to simulate the testbench design, follow these steps:
1. For Verilog testbench design:
a. Browse to the following project directory:
<variation name>_testbench/testbench_verilog/<variation name>
b. Run the following command to set up the required libraries, to compile the generated IP Functional
simulation model, and to exercise the simulation model with the provided testbench:
run_<variation_name>_tb.tcl
2. For VHDL testbench design:
a. Browse to the following project directory:
<variation name>_testbench/testbench_vhdl/<variation name>
Testbench Altera Corporation
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Simulation Model 10-4
2014.06.30