Packet classifier signals, Packet classifier common clock and reset signals, Packet classifier avalon-st interface signals – Altera Triple Speed Ethernet MegaCore Function User Manual
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Packet Classifier Signals
Packet Classifier Common Clock and Reset Signals
Table E-1: Clock and Reset Signals for the Packet Classifier
Description
Width
Direction
Signal
156.25-MHz register access reference clock.
1
Input
clk
Assert this signal to reset the clock.
1
Input
reset
Packet Classifier Avalon-ST Interface Signals
Table E-2: Avalon-ST DataIn Interface Signals for the Packet Classifier
Description
Width
Direction
Signal
The Avalon-ST input frames.
1
Input
data_sink_sop
1
Input
data_sink_eop
1
Input
data_sink_valid
1
Output
data_sink_ready
64
Input
data_sink_data
3
Input
data_sink_empty
1
Input
data_sink_error
Table E-3: Avalon-ST DataOut (Source) Interface Signals for the Packet Classifier
Description
Width
Direction
Signal
The Avalon-ST output frames.
1
Input
data_src_sop
1
Input
data_src_eop
1
Input
data_src_valid
1
Output
data_src_ready
64
Input
data_src_data
3
Input
data_src_empty
1
Input
data_src_error
Packet Classifier
Altera Corporation
UG-01008
Packet Classifier Signals
E-2
2014.06.30