Document revision history – Altera Triple Speed Ethernet MegaCore Function User Manual
Page 218
Document Revision History
Changes
Version
Date
• Added a link to the Altera website that provides the latest device support
information for Altera IP.
• Added a note in
on page 3-5—You must
configure the Arria 10 Transceiver ATX PLL output clock frequency to 1250.0
MHz when using the Arria 10 Transceiver Native PHY with the Triple-Speed
Ethernet IP core.
• Added
on page 4-19 section.
• Added new support configuration for IEEE 1588v2 feature.
• Updated the
tx_period
and
rx_period
register bits in
on page 6-16.
• Updated the timing adjustment for the IEEE 1588v2 feature PMA delay in
on page 6-17.
• Revised the control interface signal names to
reg_rd
,
reg_data_in
,
reg_
wr
,
reg_busy
, and
reg_addr
in
on page
7-3.
• Added ECC status signals in
on page 7-11 and
on page 7-19.
• Added Arria 10 Transceiver Native PHY signals in
on page 7-18.
• Added Transceiver Native PHY signal in
on page 7-23.
• Updated the following the signal diagrams:
• 10/100/1000 Ethernet MAC Signals
• 1000BASE-X/SGMII PCS Function Signals
• 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
• 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO
Buffers, with IEEE 1588v2, 1000BASE-X/SGMII PCS and Embedded PMA
Signals
• Added IEEE 1588v2 feature PHY path delay interface signals in
PHY Path Delay Interface Signals
on page 7-33.
• Updated the
Period
and
AdjustPeriod
register bits in
on page 14-5.
• Added two new conditions that the ToD synchronizer module supports in
ToD Synchronizer
chapter.
• Added three new recommended sampling clock frequencies in
ToD
Synchronizer
chapter.
• Added a new setting of 32/63 in
on page 15-2.
• Updated the
SYNC_MODE
parameter value and description in
on page 15-3.
14.0
June 2014
Additional Information
Altera Corporation
UG-01008
Document Revision History
F-2
2014.06.30