Altera Triple Speed Ethernet MegaCore Function - Manual (Page 80)

• Avalon-MM Master Translator—provides access to the registers of the following components through
the Avalon-MM interface:
• Triple-Speed Ethernet MAC
• Transceiver Reconfiguration Controller
• ToD Clock
Base Addresses
Table below lists the design example components that you can reconfigure to suit your verification objectives.
To reconfigure the components, write to their registers using the base addresses listed in the table and the
register offsets described in the components' user guides.
Table 5-1: Base Addresses of Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Components
Base Address Component
0x0000 Triple-Speed Ethernet
0x1000 Time of Day Clock
0x2000 Transceiver Reconfiguration Controller
Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files
Figure 5-2: Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Folders
<ip_library>/ethernet/altera_eth_tse_design_example
tse_ieee1588
testbench
Table 5-2: Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files
These files are located in the ..\tse_ieee1588 directory.
Description File Name
The top-level entity file of the design example for verification in hardware. tse_1588_top.v
The Quartus II SDC constraint file for use with the TimeQuest timing
analyzer. tse_1588_top.sdc
A Qsys file for the Triple-Speed Ethernet design example with IEEE
1588v2 option enabled. tse_1588.qsys
Tcl script to run testbench simulation. tb_run_simulation.tcl
Altera Corporation Triple-Speed Ethernet with IEEE 1588v2 Design Example
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5-3 Base Addresses
UG-01008
2014.06.30