Altera Triple Speed Ethernet MegaCore Function - Manual (Page 128)

Description I/O Avalon-ST Signal
Type
Name
Transmit MAC clock (2.5/25/125 MHz) for the
Avalon-ST transmit data interface. O
clk mac_tx_clk
Multiport MAC Receive Interface Signals
Table 7-14: MAC Receive Interface Signals
Description I/O Avalon-ST Signal
Type
Name
Receive data valid. When asserted, this signal
indicates that the data on the following signals are
valid:
data_rx_data _n, data_rx_sop _n, data_
rx_eop
_n, and
data_rx_error
_n.
O valid data_rx_valid _n
Receive data. O
data data_rx_data_
n
[7:0]
Receive start of packet. Asserted when the first byte
or word of a frame is driven on
data_rx_data
_n.
O startofpacket data_rx_sop_ n
Receive end of packet. Asserted when the last byte
or word of frame data is driven on
data_rx_data _
n.
O
endofpacket data_rx_eop_
n
Receive application ready. Assert this signal on the
rising edge of
data_rx_clk
_n when the user
application is ready to receive data from the MAC
function.
If the user application is not ready to receive data,
the packet is dropped or truncated with an error.
I ready data_rx_ready_ n
Receive error. Asserted with the final byte in the
frame to indicate that an error was detected when
receiving the frame. For the description of each
bit, refer to the description of bits 5 to 1 in
MAC
Receive Interface Signals on page 7-4 . Bit 4 of
this signal maps to bit 5 in the table and so forth.
O
error data_rx_error_
n
[4:0]
Multiport MAC Transmit Interface Signals
Table 7-15: MAC Transmit Interface Signals
Description I/O Avalon-ST Signal
Type
Name
Avalon-ST Signals
Altera Corporation Interface Signals
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7-13 Multiport MAC Receive Interface Signals
UG-01008
2014.06.30