Altera Triple Speed Ethernet MegaCore Function - Manual (Page 180)

11 Software Programming Interface
2014.06.30
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Driver Architecture
Figure 11-1: Triple-Speed Ethernet Software Driver Architecture
TX SGDMA
RX SGDMA
Memory
Client
Apps
Interniche
Stack
TSE Driver
Control Interface
TX FIFO (2)
RX FIFO (2)
TX Descriptor
RX Descriptor
TSE MAC
Descriptor Memory (1)
Nios II CPU
TX Path
RX Path
Avalon -MM Interface
Setup
Descriptors
MII/GMII
MII/GMII
Pr
oc
ess
&
W
rit
e
Back
St
atus
Pr
oc
ess
&
W
rit
e
Back
St
atus
Notes to Figure 11–1 :
1. The first n bytes are reserved for SGDMA descriptors, where n = (Total number of descriptors + 3) × 32.
Applications must not use this memory region.
2. For MAC variations without internal FIFO buffers, the transmit and receive FIFOs are external to the
MAC function.
ISO
9001:2008
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