Altera Triple Speed Ethernet MegaCore Function - Manual (Page 155)

Figure 7-11: Receive Operation—MAC Without Internal FIFO Buffers
mac_rx_clk_0
data_rx_data_0[7:0]
data_rx_sop_0
data_rx_eop_0
data_rx_ready_0
data_rx_error_0[5:0]
data_rx_valid_0
pkt_class_data_0[3:0]
pkt_class_valid_0
00 00 03 04 05 06 07 08 09 10 10 10 10 00
00
00 10 0
Figure 7-12: Invalid Length Error During Receive Operation—MAC With Internal FIFO Buffer
ff_rx_clk
ff_rx_data[31:0]
ff_rx_sop
ff_rx_eop
ff_rx_rdy
ff_rx_dval
ff_rx_dsav
rx_frm_type[3:0]
rx_err_stat[17:0]
rx_err[5:0]
ff_rx_mod[1:0]
00000000 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007
00 1 0
00000 00000 005DD 00000
00 00 03 00
00 3 0
Figure 7-13: Invalid Length Error During Receive Operation—MAC Without Internal FIFO Buffers
mac_rx_clk_0
data_rx_data_0[7:0]
data_rx_sop_0
data_rx_eop_0
data_rx_ready_0
data_rx_error_0[5:0]
data_rx_valid_0
pkt_class_data_0[3:0]
pkt_class_valid_0
00 00 03 04 05 06 06 07 08 09 09 09 09 09 00
00 00 01
00 10 0
Interface Signals Altera Corporation
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UG-01008
Avalon-ST Receive Interface 7-40
2014.06.30