Altera Triple Speed Ethernet MegaCore Function User Manual
Page 139
Description
I/O
Name
Reference clock for the dynamic reconfiguration controller. If you
use a dynamic reconfiguration controller in your design to
dynamically control the transceiver, both the reconfiguration
controller and the MegaCore function require this clock. This clock
must operate between 37.5–50 MHz. Tie this clock low if you are
not using an external reconfiguration controller.
This signal is not present in PMA blocks implemented in Stratix V
devices with GX transceivers.
I
reconfig_clk
Driven from an external dynamic reconfiguration controller.
Supports the selection of multiple transceiver channels for dynamic
reconfiguration.
For PMA blocks implemented in Stratix V devices with GX
transceivers, the bus width is [139:0]. For more information about
the bus width for PMA blocks implemented in each device, refer to
the Dynamic Reconfiguration chapter of the respective device
handbook.
I
reconfig_togxb[n:0]
Connects to an external dynamic reconfiguration controller. The
bus identifies the transceiver channel whose settings are being
transmitted to the reconfiguration controller. Leave this bus
disconnected if you are not using an external reconfiguration
controller.
For more information about the bus width for PMA blocks
implemented in each device, refer to the Dynamic Reconfiguration
chapter of the respective device handbook.
O
reconfig_fromgxb[n:0]
Driven from an external dynamic reconfiguration controller. This
signal will indicate the busy status of the dynamic reconfiguration
controller during offset cancellation. Tie this signal to 1'b0 if you are
not using an external reconfiguration controller.
This signal is not present in PMA blocks implemented in Stratix V
devices with GX transceivers.
I
reconfig_busy
For more information on the signals, refer to the respective sections shown in
Interface Signals
Altera Corporation
UG-01008
SERDES Control Signals
7-24
2014.06.30