Altera Triple Speed Ethernet MegaCore Function - Manual (Page 153)

Table 7-42: References
Section Interface Signal
TBI Interface Signals on page 7-16 Ten-bit interface
Status LED Control Signals on page 7-17 Status LED signals
SERDES Control Signals on page 7-17 SERDES control signals
Arria 10 Transceiver Native PHY Signals on page 7-18 Arria 10 Transceiver Native PHY signals
1000BASE-X/SGMII PCS and PMA Signals
Figure 7-9: 1000BASE-X/SGMII PCS Function and PMA Signals
Reset
Signals
reset _rx_clk
reset _tx_clk
reset
set _10
set _100
set _1000
hd_ena
SGMII
Status
Signals
Status
LED
Signals
led _an
led _crs
led _col
led _char _err
led _link
led _disp _err
led _an
rx_clk
tx_clk MII /GMII
Clock
Signals
rx_clkena
tx_clkena Clock
Enabler
Signals
GMII
Signals gmii_rx_d[7:0]
gmii_rx_dv
gmii_rx_err
gmii_tx_d[7:0]
gmii_tx_en
gmii_tx_err
8
8
mii_rx_d[3:0]
mii_rx_dv
mii_rx_err
mii_col
mii_crs
mii_tx_d[3:0]
mii_tx_en
mii_tx_err
MII
Signals
4
4
PCS
Control
Interface
Signals
clk
address [4:0]
read
write
readdata [15 :0]
writedata [15 :0]
waitrequest
16
16
5
SERDES
Control
Signals
pcs _pwrdn _out
gxb _pwrdn _in
gxb _cal _blk_clk
reconfig _clk
reconfig _togxb
reconfig _fromgxb
rx_recovclkout
1.25 Gbps
Serial Signals
ref_clk
rx_p
tx_p
reconfig_busy
1000BASE-X/SGMII PCS Function With Embedded PMA
Notes to Figure 7–9 :
1. The clock enabler signals are present only in SGMII mode.
2. The SERDES control signals are present in variations targeting devices with GX transceivers. For Stratix
II GX and Arria GX devices, the reconfiguration signals— reconfig_clk , reconfig_togxb , and
reconfig_fromgxb
—are included only when the option, Enable transceiver dynamic reconfiguration,
is turned on. The reconfiguration signals—
gxb_cal_blk_clk
,
pcs_pwrdwn_out
,
gxb_pwrdn_in
,
reconfig_clk , and reconfig_busy —are not present in variations targeting Stratix V devices with GX
transceivers.
Interface Signals Altera Corporation
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1000BASE-X/SGMII PCS and PMA Signals 7-38
2014.06.30