Altera Triple Speed Ethernet MegaCore Function - Manual (Page 137)

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
Figure 7-5: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII PCS
With Embedded PMA Signals
Status
LED
Signals
led_an
led_crs
led_col
led_char _err
led_link
led_disp_err
PHY
Management
Signals
mdio_in
mdc
mdio_oen
mdio_out
1.25 Gbps
Serial Signals
ref_clk
rx_p
tx_p
Reset
Signal
reset
ECC Status
Signal
mac_eccstatus[1:0]
Transceiver
Native PHY
Signal
cdr_ref_clk_n
Pause and Magic
Packet Signals
xon_gen
xoff_gen
magic_wakeup
magic_sleep _n
n
2
MAC Transmit
Interface Signals
ff_tx_crc _fwd
ff_tx_data[DATAWIDTH -1:0]
ff_tx_eop
ff_tx_err
ff_tx_sop
ff_tx_wren
tx_ff_uflow
ff_tx_rdy
ff_tx_septy
ff_tx_mod[1:0]
ff_tx_a_full
ff_tx_a_empty
ff_tx_clk
ff_rx_clk
MAC Receive
Interface Signals
ff_rx_data[DATAWIDTH -1:0]
ff_rx_mod[1:0]
ff_rx_eop
ff_rx_sop
rx_err[5:0]
rx_err_stat[17:0]
rx_frm_type[3:0]
ff_rx_dsav
ff_rx_rdy
ff_rx_dval
ff_tx_a_full
ff_tx_a_empty
n
2
6
18
4
SERDES
Control
Signals
pcs _pwrdn_out
gxb_pwrdn_in
gxb_cal_blk_clk
reconfig_clk
reconfig_togxb
reconfig_fromgxb
rx_recovclkout
32
32
MAC Control
Interface
Signals
clk
reg_addr[7:0]
reg_rd
reg_wr
reg_data_out[31:0]
reg_data_in[31:0]
reg_busy
8
10/100/1000 Ethernet MAC and 1000BASE-X/SGMII PCS
with Embedded PMA
Note to Figure 7–5 :
1. The SERDES control signals are present in variations targeting devices with GX transceivers. For Stratix
II GX and Arria GX devices, the reconfiguration signals—
reconfig_clk
,
reconfig_togxb
, and
reconfig_fromgxb
—are included only when the option, Enable transceiver dynamic reconfiguration,
is turned on. The reconfiguration signals— gxb_cal_blk_clk , pcs_pwrdwn_out , gxb_pwrdn_in ,
Interface Signals Altera Corporation
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10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 7-22
2014.06.30