Altera Triple Speed Ethernet MegaCore Function - Manual (Page 142)

Description Width I/O Signal
When asserted, this signal indicates that
rx_ingress_timestamp_96b_data
contains valid timestamp.
For all receive frame, the MAC asserts this
signal in the same clock cycle it receives
the start of packet (
avalon_st_rx_
startofpacket
is asserted).
1 O
rx_ingress_timestamp_96b_valid
Carries the ingress timestamp on the
receive datapath. Consists of 48-bit
nanoseconds field and 16-bit fractional
nanoseconds field.
The MAC presents the timestamp for all
receive frames and asserts this signal in the
same clock cycle it asserts
rx_ingress_
timestamp_64b_valid .
64 O
rx_ingress_timestamp_64b_data
When asserted, this signal indicates that
rx_ingress_timestamp_64b_data
contains valid timestamp.
For all receive frame, the MAC asserts this
signal in the same clock cycle it receives
the start of packet (
avalon_st_rx_
startofpacket is asserted).
1 O
rx_ingress_timestamp_64b_valid
IEEE 1588v2 TX Timestamp Signals
Table 7-30: IEEE 1588v2 TX Timestamp Interface Signals
Description Width I/O Signal
A transmit interface signal. This signal
requests timestamp of frames on the TX
path. The timestamp is used to calculate
the residence time.
Consists of 48-bit seconds field, 32-bit
nanoseconds field, and 16-bit fractional
nanoseconds field.
96 O tx_egress_timestamp_96b_data_n
Altera Corporation Interface Signals
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7-27 IEEE 1588v2 TX Timestamp Signals
UG-01008
2014.06.30