Simulate the system, Programming an fpga device – Altera Triple Speed Ethernet MegaCore Function User Manual
Page 27
Generating a design example can increase processing time.
Note:
You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating
your IP core instance into your design, you must make appropriate pin assignments. You can create a virtual
pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready
to map the design to hardware.
Related Information
•
More information about the MegaCore function simulation model.
•
More information about the Quartus II software, including virtual pins.
Simulate the System
During system generation, Qsys generates a functional simulation model—or design example that includes
a testbench—which you can use to simulate your system in any Altera-supported simulation tool.
Related Information
•
More information about the latest Altera-supported simulation tools.
•
More information in volume 3 of the Quartus II Handbook about simulating Altera IP cores.
•
More information in volume 1 of the Quartus II Handbook about simulating Qsys systems.
Compiling the Triple-Speed Ethernet MegaCore Function Design
Before you begin
Refer to
on page 8-1 chapter before compiling the Triple-Speed Ethernet MegaCore
function design.
To compile your design, click Start Compilation on the Processing menu in the Quartus II software. You
can use the generated .qip file to include relevant files into your project.
Related Information
More information about compilation in Quartus II software.
Programming an FPGA Device
After successfully compiling your design, program the targeted Altera device with the Quartus II Programmer
and verify the design in hardware. For instructions on programming the FPGA device, refer to the Device
Programming section in volume 3 of the Quartus II Handbook.
Related Information
Getting Started with Altera IP Cores
Altera Corporation
UG-01008
Simulate the System
2-8
2014.06.30