Phy management signals – Altera Triple Speed Ethernet MegaCore Function User Manual

Page 125

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Description

I/O

Name

RGMII control input signal. Expects

gm_rx_dv

on the positive edge of

rx_clk

and a logical derivative of (

gm_rx_dv XOR gm_rx_err)

on the

negative edge of

rx_clk

.

I

rx_control

MII Transmit

MII transmit data bus.

O

m_tx_d[3:0]

Asserted to indicate that the data on the MII transmit data bus is valid.

O

m_tx_en

Asserted to indicate to the PHY device that the frame sent is invalid.

O

m_tx_err

MII Receive

MII receive data bus.

I

m_rx_d[3:0]

Assert this signal to indicate that the data on the MII receive data bus
is valid. Keep this signal asserted during frame reception, from the first
preamble byte until the last byte of the CRC field is received.

I

m_rx_en

The PHY asserts this signal to Indicate that the receive frame contains
errors.

I

m_rx_err

MII PHY Status

Collision detection. The PHY asserts this signal to indicate a collision
during frame transmission. This signal is not used in full- duplex or
gigabit mode.

I

m_rx_col

Carrier sense detection. The PHY asserts this signal to indicate that it
has detected transmit or receive activity on the Ethernet line. This
signal is not used in full-duplex or gigabit mode.

I

m_rx_crs

PHY Management Signals

Table 7-11: PHY Management Interface Signals

Description

I/O

Name

Management data input.

I

mdio_in

Management data output.

O

mdio_out

An active-low signal that enables

mdio_in

or

mdio_out

. For more

information about the MDIO connection, refer to

MDIO Connection

on page 4-21.

O

mdio_oen

Management data clock. Generated from the Avalon-MM interface
clock signal,

clk

. Specify the division factor using the Host clock

divisor parameter such that the frequency of this clock does not exceed
2.5 MHz. For more information about the parameters, refer to

Ethernet

MAC Options

on page 3-2.

A data bit is shifted in/out on each rising edge of this clock. All fields
are shifted in and out starting from the most significant bit.

O

mdc

Interface Signals

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PHY Management Signals

7-10

2014.06.30

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